1. Field of the Invention
The present invention relates generally to computer system hardware. More particularly, the present invention relates to a hardware architecture for control and status registers within a computer system processor.
2. Art Background
Computer systems frequently make use of registers for temporary storage of data or for control purposes. Registers are commonly constructed so that multiple bits of information may be stored at the same time, typically ranging from one to four bytes. Data in the form of logical zeros and ones generated by the computer's processor may be stored in the register, and then subsequently re-read by the processor. In controlling a computer's operation, operating systems frequently require that a single bit, within a collection of bits stored in a multiple bit register, be altered without affecting the remaining bits. In such a case, the operating system will execute a read-modify-write cycle, whereby the CPU reads information contained in the storage register, then modifies the contents and subsequently writes the modified contents back into the register. The read-modify-write operation, permits the processor to set or clear bits of a particular control parameter as needed in subsequent data processing or computing operations.
Execution of a read-modify-write cycle is commonly used in single processor systems. However, in a multiple processor environment where more than one master device has equal opportunity to access a register, there exists a substantial likelihood that one master will overwrite, modify, alter, or otherwise interfere with the contents of the register previously stored by another master device. Referring briefly to FIG. 1, two processors sharing a storage register are shown, wherein both processors are concurrently performing read-modify-write cycles upon a single register. From FIG. 1, it is seen that when Master B completes its final write operation, Master B will have nullified Master A's write operation. A crucial requirement of multiple processor systems is that information stored by a particular master is not subsequently undone by another master. The condition of the contents of a particular register, being consistent with the master device causing such contents to be stored in that register, is known as "coherence". Coherence in a multiple processor environment where more than one master has the opportunity to modify information stored in a register is of concern primarily in the context of cache memory architectures. In a multiple processor architecture incorporating cache memories, cache consistency with respect to a particular master is of paramount concern.
In the prior art, a predominant method of preventing cache coherence problems is to invoke a so called "mutual exclusion lock", as shown in FIG. 1a. A mutual exclusion lock is a semaphore where, in software, a particular master obtains, prior to accessing a particular register, ownership of a signal or flag which permits the accessing master, and only that accessing master, to engage and control that register. A mutual exclusion lock is typically invoked by a master executing an exchange operation with a hardware register comprising the flag. The master reads the contents of the flag register and thereafter loads some non-zero value into the register, where both read and write operations are performed such that no other master can read or write to that register during the pendency of the exchange operation. The master then tests the value of the contents read from the register during the exchange: if the register contents equal "0", then the lock was "free", and may now be claimed by the master; if the register contents equal some non-zero value then the lock is "not free", and the master is denied use of that lock. The master would typically continue to perform exchange and test operations until the tested value was "0", indicating the lock is "free". A lock is released by the master having control of the lock writing a "0" into the flag register. For example, as shown in FIG. 1a, the lock is set when a master executes an exchange operation, the master storing some non-zero value &lt;lock.sub.-- busy&gt;. The master then tests the value of the contents previously stored in the lock register against a reference value &lt;lock.sub.-- free&gt; to see if the lock was "free". If the previously stored contents equals &lt;lock.sub.-- free&gt;, the master will determine it is the owner of the lock.
Controlling the mutual exclusion lock permits a processor to access and store information in a register without concern that information stored will be later corrupted due to an unexpected access by another processor. Furthermore, only the masters which claimed the lock by setting the flag can release the lock by clearing the flag. Mutual exclusion locks are well known in the prior art, and several software algorithms exist which produce the lock function. In multiple processor systems, there exist many such mutual exclusion locks and the operating system software uses such locks frequently to indicate when critical code is being executed, or when critical registers are being accessed. However, the use of mutual exclusive locks requires significant additional processing time as well as additional code space in order to effect the lock function. In speed critical computation, use of multiple locks can substantially hamper or otherwise diminish system performance.
As will be discussed below, the present invention discloses a simple register architecture which ensures coherence between masters and data stored in system storage registers in a multiple processor environment, without the need for time intensive software interlock mechanisms provided in the prior art. Furthermore, the present invention permits one or more individual bits of a shared register to be accessed and modified directly and simultaneously without requiring software interlocks as in the prior art.